EE447/EE547
VLSI Design
Fall 2001

Instructor Abul N. Khondker
Office CAMP 134, Tel: 268-2127
Office Hours MWF 10:00-12:00 pm Or, by appoinments
Text

Required: Principles of CMOS VLSI Design: A systems Perspective by Neil Weste and Kamran Eshraghian (1993)

Recommended: Verilog HDL: A guide to digital design and synthesis by Samir Pa1nitkar, Sunsoft Press Printice Hall) (1996)

Software
  • SmartSpice on rs6000 UNIX system
  • LASI Pro 5.1 Download locally
  • LASI pro 5.0. Or, you can download it from here
Prerequisites EE241 and EE341
Course Content

  • Introduction
  • MOS transistor theory, P- and NMOS, CMOS devices, basic device equations
    Inverters and transmission gates, SPICE simulation
  • CMOS processing, Manufacturing Technology, Design rules LASI pro CAD tool
  • Circuit characterization and performance estimation, switching characteristics
    (rise and fall times, gate delays), power dissipation
  • CMOS circuit and Logic Design: gates, dynamic logic, registers and latches
  • Students enrolled in EE547 will be responsible for additional advanced materials
Homework There will be approximately 7-10 assignments throughout the session.
Each assignment (homework and/or project) will be graded on a scale of 0 to 10. Unsatisfactory work will be must be redone with some penalty of points.
Midterm Exam

Take home exam. The test will be given on October 12th. Due date: October 16th. (date may change)

Grading policy The course grade will be determined from a weighted average on the normalized homework+project and exam grades. The weights will be: Homework+project 30, Midterm exam - 20, Final oral exam - 15, and Final project 35
The following scale will be used to convert numerical grades to letter grade:
A(90-100 ), B+(85-89.9 ), B(80-84.9 ), C+(75-79.9 )
C(70-74.9 ), D+(65-69.9 ), D(60-64.9 ), F(0-59.9 ).
MOS Theory In *.pdf format
Supplementary notes on MOS Theory In *.pdf format
Some Selected topics for the VLSI course

    • Help on PSpice

    pSpice Files:

    inv_r.cir-An inverter with a resistive load
    inv_ed.cir-An NMOS inverter with a depletion load
    inv_cmos.cir-A CMOS inverter
    tran.cir-Transient Analysis....circuit contains a transmission gate
    mux2-1_1.cir-Delays in a CMOS transmission gate 2-1_MUX circuit
    mosfet.cirMOSEFT model used in this course

    SmartSpice Files (examples):

    inv_r.in-An inverter with a resistive load
    inv_ed.in-An NMOS inverter with a depletion load
    inv_cmos.in-A CMOS inverter
    tran.in-Transient Analysis....circuit contains a transmission gate
    tran_inv_cmos.in-Transient Analysis....circuit contains an inverter

    Download these files for the BSIM3 models of NMOS and PMOS devices.

    modelcard.nmos-BSIM model for NMOS
    modelcard.pmos-BSIM model for PMOS
    nmos_curves.in-BSIM I-V curves for NMOS
    pmos_curves.in-BSIM I-V curves for NMOS

    Homework

    Homework #1 In *.pdf format. Updated Sept 16, 2001
    Homework #2 In *.pdf format. Due date Oct 4, 2001
    For help on problem 2 of Homework 2, Click here.

    Lasi Pro 5.1

    Download Lasi5 (clarkson Univ version). Save on a floppy and run install.
    Getting started with Lasi 5.1
    Color codes for various layers in the LASI software.
    CMOSN Design Rules for DRC

    tlc files:Copy all of the files on a floppy and tlcin 4-1mux_k file. Answer yesto all questions and do not use the .tlc extension This will tlcin the other 3 files that are used as cells in 4-1mux_k.

    4-1mux_k.tlc
    2-1mux_k.tlc
    con_k.tlc
    inv_k.tlc
    Some Selected topics for the VLSI course

    Here are two layout examples of the 4-bit binary counter:

    wsl2.tlc - by Wu, Love and Shashi
    ripple2.tlc - by Chen, Fan and Zhou

    Some examples....(good designs) by Daryl Seitzer:

    2 input Nor gate
    2 input Xor gate

    Some examples....(designs that have room for improvements by using less "room"):

    2 input Nor gate
    2 input Xor gate

    Some more examples....(what do you think about these?):

    2 input Nor gate
    2 input Xor gate

    4 bits Serial to parallel register by Huzaifa, Rishi and Sachin

    4 bit Ser_2_parallel register

    Verilog notes-1 -- part of this is taken from a Verilog training Manual from Cadence
    Verilog notes-2

    ripple.v - from Verilog HDL by Samir Palnitkar
    ripple1.v - negative edge-triggered D-flipflop
    ripple2.v - negative edge-triggered T-flipflop

    The following files are variations of ripple.v that describes the 4-bit ripple carry counter.

    rip.v - Behavioral level abstration
    rip1.v - Gate and behavioral level abstration
    rip2.v - Dataflow level abstration
    rip3.v - Switch level abstration
    test1.v - 2 input AND