The purpose of this part of the course is to:

• understand design Methodologies . The are two basic types:

1. Bottom-Up Design Flow
2. Top-Down Design Flow
   

• understand HDL (Hardware Description Language)
  
  

Why Use an HDL?

• Designers can explore various options easily

• It reduces cost

• It makes it easier to design large and complex systems - designers do not need to manually place gates to build circuits.
  
  

Key Features of HDL

• HDL contains some high-level programming constructs along with constructs to describe the connectivity of hardware design

• It allows the designer to describe various levels of abstractions without choosing a specific fabrication technology

• It can describe functionality as well as timing

• Concurrency -- can perform multiple tasks at the same time

• Time -- This is not built into other programming languages

• Easy to learn and easy to use
  
  
  
  
  
  

Simulation Algorithms

Time Driven

• Each circuit element is evaluated at the end of each time point

• Inefficient because at any time only 2-10 percent of the

• circuit need to be evaluated
  

Event Driven

• Only those circuits that might cause a change are simulated

• Evaluates when necessary

Demand Driven

• Further refines "Evaluates when necessary"
  
  

Different Levels of Abstractions

• Architectural/Algorithmic level
• Dataflow level
• Gate level
• Switch level

Architectural/Algorithmic level

• The system is described in terms of the algorithms it performs

• The aim is to study the data flow of the system and potential bottleneck

Dataflow level

• Describes the flow of data and control signals between various functional blocks

• Schedules assignment at clock edge

Gate level

• Interconnection of switching elements (or gates) to check functionality, performance or timing of design

Switch level

• Describes logic behavior of transistor circuits

• Evaluates conflicts caused by bidirectional pass transistors, signal strengths of multiple elements driving a net
  

• It uses a combination of behavioral and dataflow constructs

• This is the most popular level because logic synthesis tools can create gate-level netlist from the RTL level design
  
  
  
  

Modules

• This is the basic building block in Verilog

• Can be an element or collection of lower level blocks

module add4 (s,c4,ci,a,b);

    input [3:0] a,b;

    input ci;

    output [3:0]s;

    output c4;

    wire [2:0] co;

        add a0 (co[0],s[0],a[0],b[0],ci);

        add a1 (co[1],s[1],a[1],b[1],co[0]);

        add a2 (co[2],s[2],a[2],b[2],co[1]);

        add a3 (c4,s[3],a[3],b[0],co[2]);

endmodule

Instances

• A modules provides a template
• Objects can be created from a template by a process called instantiation

  The objects are called instances
  
  
  

Examples of instantiation

// NOT Gate logic simulation

`timescale 1 us / 10 ns

module inverter(IN,OUT);

     output OUT;

          not #(1,3) inv1(OUT,IN); // gate instantiation

endmodule

Note: not is a verilog-provided primitive

//NAND Gate simulation model

`timescale 1 us / 10 ns

module nand_gate(IN1,IN2,OUT);

     input IN1,IN2;

     output OUT;

        // gate instantiation

        nand #(1,2) nand1(OUT,IN1,IN2);

endmodule



module Top;

     wire C ;

     reg A,B;

      nand_gate nand1(A,B,C); // Instantiation of lower block

     // Stimulate the input

     initial

     begin

     A=0; B=0;

     #5 B=1;

     #5 B=0; A=1; 

     #5 B=1; 

     #5 A=0;

     #5 B=0;

     end

endmodule