*inv_CMOS.in
*An CMOS inverter circuit


* Transistor measurements
.param lg = 2.0u   ; default gate length
.param ld = 3.5u ; default drain length
.param ls = 3.5u ; default source length

.param inv_nw=3um
.param inv_pw="2*inv_nw"

* Calculated MOS model parameters
.func as(w, ls) ls*w
.func ad(w, ld) ld*w
.func ps(w, ls) 2*ls+w
.func pd(w, ld) 2*ld+w

* Global nodes
.global vdd
.global vss

* Model for NMOS FET
.model ndev nmos(level=2 tox=150e-10 vto=1.0 kp=60e-6 gamma=0.37 cgbo=200p 
+ cgso=600p cgdo=600p cj=200u cjsw=400p mj=0.5 mjsw=0.3 pb=0.7)

* Model for PMOS FET
.model pdev pmos(level=2 tox=150e-10 vto=-1.0 kp=30e-6 gamma=0.37 cgbo=200p 
+ cgso=600p cgdo=600p cj=200u cjsw=400p mj=0.5 mjsw=0.3 pb=0.7)

* Inverter for Circuit
.subckt inv a y PARAMS: wn=inv_nw wp=inv_pw lg=lg ld=ld ls=ls
mn y a vss vss ndev w=wn l=lg as="as(wn, ls)" ad="ad(wn, ld)" ps="ps(wn, ls)" 
+ pd="pd(wn, ld)"
mp y a vdd vdd pdev w=wp l=lg as="as(wp, ls)" ad="ad(wp, ld)" ps="ps(wp, ls)"
+ pd="pd(wp, ld)"
.ends inv

* Main input file

xinv in out inv lg=1.0u
vin in 0 dc 1

* Global power rails
vdd vdd 0 5
vss vss 0 0

.dc vin 0 5.0 0.05
.probe
.end

