3.1.2 Comments
// This is a comment line
/* So are these
lines */
3.1.3 Operators
For more on operators see Table 6-1 in section 6.4. Operators types can be
arithmatic, logical, relational, equality, bitwise, reduction, shift,
shift, concatenation, or conditional. Depending on the number of
operands, the operators can be classified as unary,
binary and ternary.
Examples:
a = ~b; // Bitwise, unary negation operator
a = b && c; // Logical, binary operator
d = !e; // Logical, unary negation operator
a = b ? c : d; // Conditional, ternary
operator
3.1.4 Number Specification
Sized numbers: <size>'<base formal><number>
Examples:
4'b1111 // 4-bit binary number
12'habc // 12-bit hexadecimal number
16'd255 // 16-bit decimal number
Unsized number
Examples:
952 // 32-bit (default) decimal (default) number
'habc //32-bit hex number
'o72 // 32-bit octal
X or Z values
In verilog, an unknown and a high impedance value is represented by
x and z, respectively.
6'hx // 6-bit unknown hex number
3.1.5 Strings
"Hello world" // is a string
3.1.6 Identifiers and Keywords
Identifiers are names given to objects. They cannot start with $ or
a number. Keywords are special identifiers that are reserved to define
the Verilog language constructs. Keywords are in lower case. See
Appendix C.
3.2 Data types
Four values and 8 strengths
| Condition in Hardware | |
| Logic zero, false | |
| Logic one, true | |
| unknown | |
| high impedance, floating state |
Values 0 and 1 can have 8 strength level (see Table
3-2)
3.2.2 Nets
They represent connection between hardware elements and they are
declared (primarily) with keyword wire. Default is one-bit value unless
declared as vectors.
Examples:
wire a,b,c; // Declare three wires for a given circuit
wire d=1'b1; // d is a 1-bit net with
a fixed value of 1
3.2.3 Registers
Registers are data storage elements. Unlike net, registers do not
need drivers or driver circuits. The values can be changed at anytime.
Keyword is reg.
Examples:
reg reset;
initial //
begin
reset = 1b'1; // reset is initialized to 1
#100 reset = 1b'0; // after 100 time units, reset is changed to 0
end
3.2.4 Vectors
Nets (like wires) and reg data types can be mutiple bit widths (or
vectors)
Examples:
wire a; // 1-bit, by default
wire [7:0] bus; // 8-bit bus, bus[7] is the MSB, bus[0] is the LSB
reg [0:31] c // 32-bit vector register
One can address vectors as follows.
Examples:
bus[4] // bit #4 of vector bus defined above
bus[2:0] // 3 least significant bit of vector bus
c[0:3] // 4 MSBs of register c
3.2.5 Integer, Real and time register data
types
Integer and real numbers
Default width of an integer is al least 32 bits.
Real numbers can be in decimal notation (3.14159) or in scientific
notation
Examples:
integer counter, i; /* the variable counter can now be assigned an interger value */
real pie;
initial
begin
counter=1;
pie=3.14159; // Greek pi
end
i = pie; // i gets the value of 3 (rounded
value of pi)
Time
In verilog a special time register is used to store simulation time. The width
of the time register is at least 64 bits. The system
function $time is used to get the current time
Examples:
time begin_time;
initial
begin_time = $time; //save the current
simulation time
3.2.6 Arrays
Arrays are multiple elements that can be 1-bit or n-bit wide. Arrays are
allowed for reg, integer, time and vector register
data types.
Examples:
reg bool1 [31:0]; // 32 1-bit array
reg [31:0] bool2 ; // one 32-bit vector
reg [7:0] bool3 [5:0] // array of 6
bool3, each 8-bit wide
Read Sections 3.2.7-3.2.9
3.3 System Tasks and Compiler directives
3.3.1 System Tasks
Displaying information: using $display
Example:
$dislay("Hello World"); // Display the string in quotes
$display($time); //Display the current
simulation time
Also see Table 3-4
Monitoring information: using $monitor
Example:
initial
begin
$monitor($time, "value of signal = %b reset %b" clock, reset) end
/* Here clock and reset are displayed
in binary Also see Table
3-4 */
Note, if there are more than one $monitor statements, only the last
one will be the active statement. Also see $monitoron
and $monitoroff.
Stopping and finishing in a simulation
Example:
initial
begin
clock =0;
reset = 1;
....
....
#100 $stop; //This suspends the simulation at time=100
#900 $finish; //This terminates the simulation at time=900
end
3.3.2 Compiler Directives
All compiler directives in Verilog are defined using
the `<Keyword>
construct (see Appendix C.3). Here we learn about two of these
directives:
`define is used to define
text macros.
Example:
`define word_size 32
`define S $stop; // A $stop will be
substituted whereever S appreas
`include directive allows you to include entire contents of s Verilog source
file in another Verilog file during compilation
Example:
// Include the file header.v in the present circuit.v file
`include header.v
…..
…..
<Verilog codes in file circuit.v>
…..
Also read `timescale and 'ifdef in chapter 9.