EE 491/694 (or EE 447/547)

VLSI Design, Spring 2008

 

I. Course Description

An advanced project-oriented course on the design of Very Large Scale Integrated Circuits. Students working in teams will design a CMOS integrated circuit and write a final report. The course will require the use of SPICE, HDL languages (Verilog or VHDL) and several VLSI layout tools. Substantial independent work on advanced topics will be required (for students enrolled in EE547)

 

II. Prerequisites

EE241 and EE341

 

III. Textbook

Principles of CMOS VLSI Design: A Circuit & Systems Perspective

Neil H. Weste & David Harris, Publisher: Addison-Wesley  (2005) (required)

ISBN 0-321-14901-7

Application-Specific Integrated Circuits – An Introduction to VHDL and Verilog HDL

Smith, Michael J. S. , Publisher: Addison-Wesley  (2000) (required)

ISBN 0-201-73357-9

Both of these books will be available at the University Bookstore with a single ISBN 0-321-29925-6.

 

IV. Course Topic Outline                                       

1.       Introduction MOS transistor theory, P- and NMOS, CMOS devices, basic device equations 

2.       Inverters and transmission gates, 

3.       SPICE simulation

4.       CMOS processing, Manufacturing Technology, Design rules  LASI pro CAD tool

5.       Circuit characterization and performance estimation, switching characteristics,

                        (rise and fall times, gate delays), power dissipation

6.       CMOS circuit and Logic Design: gates, dynamic logic, registers and latches

7.       Testability

V.  Course Policies and Grading

  1. There will be approximately 7-10 assignments throughout the session.
  2. Each assignment (homework and/or project) will be graded on a scale of 0 to 10. Unsatisfactory work must be redone with some penalty of   points.
  3. Take home exam.
  4. The course grade will be determined from a weighted average on the normalized homework, project and exam grades.  The weights will be:  

                                                                                                                      

·         Homework/project  - 30

·         Midterm exam - 20

·         Final exam (may be an oral exam) - 15

·         Final project 35

 

5.   The following scale will be used to convert numerical grades to letter grade:  A(90-100 ), B+(85-89.9 ), B(80-84.9 ), C+(75-79.9 ), C(70-74.9 ), D+(65-69.9 ), D(60-64.9 ), F(0-59.9 ).

               

VI.  Instructor

                Dr. Abul Khondker

                CAMP 134, phone: x-2127, khondker@clarkson.edu

                Office hours:  MWT 10:30-12:00 noon, TTh 11:00-12:00 noon

 

 

Software

·   Install ModelSim. Remember to choose the starter version (Free) and Verilog during the install proceedure.

Follow the procedure in the webpage to obtain a license for your PC.

·  SmartSpice is available on Network PCs around the campus.

·  Electric – Staticfreesoft

ü      You can download Electric from their website or from here.

ü      Extract it in a folder named C:\Electric.

ü      Make a shortcut of electricBinary-8.06.jar on the desktop or in the Startmenu of your PC.

ü      Right click on the shortcut icon that you have created, choose the properties and modify the target using the following command:

            C:\WINDOWS\system32\java.exe -classpath "C:\Electric\electricBinary-8.06.jar;electricIRSIM-8.06.jar;electricJava3D-8.06.jar;electricJMF-8.06.jar" com.sun.electric.Launcher

For details visit the Staticfreesoft webpage and read how to set up JAVA and Electric on your computer. 

 
 
Lecture notes:(adopted and modified from
David Harris’ website)
 
EE447_lecture1 Introduction
EE447_lecture2 Circuits and Layout
EE447_lecture3 CMOS Transistor Theory
EE447_lecture3a Nonideal Effects
EE447 Lecture4 DC and Transient Response
EE447 Lecture5 Logical Effort
EE447 Lecture6 Wires
EE477 Lecture7 Combinational Circuits
EE477 Lecture8 Circuit Families
EE477 Lecture9 Sequential Circuits
EE477 Lecture10 Design for Testability
 
 

Homework

 

Homework 1: (due date: Jan 22)

Exercises 1.3, 1.4, 1.7a, 1.11, 1.12, 1.14 & 1.16 (EE 447 and EE 547)

                  1.17, 1.18 (EE 547 only)

 

Homework 2: (Due date: January 31) (You can work in a group of two people) 
 
1. Design and layout a 3:2 priority encoder (see Exercise 1.7b of your textbook) using the 
JAVA-Electric CAD software. For the inverter, the widths of the NMOS transistor should be 
6l and the widths of the PMOS transistor should be 12l.  For other gates, use widths for the 
FETs such that the pull-up and the pull-down paths have strengths comparable to that of the 
inverter. In the spice deck add 0.1pF of capacitive loads  t each output. Simulate using 
SmartSpice and show the functionality of the encoder. Using the “.measure” statement, 
estimate the 50%-50% delay between the inputs and output and the 10%-90% Rise and  90%-10%  
all delays of the output waveforms. What happens if the load capacitance is increased to 
0.1pf and 1.0pf?
 
2. Layout a positive-edge triggered D flip-flop (DFF) (see Fig 1.31 and Fig 1.73 of your 
textbook) using the JAVA-Electric CAD software. The widths of the NMOS transistor should be 
6l and the widths of the PMOS transistor should be 12l.  In the spice deck use a 0.1pF of 
capacitive load at the output, Q. Simulate using Spice show the functionality of DFF. Use 
a clock with rise and fall times equaling 0.1ns each and a period of 1ns. Design a testbench 
for the data input and clock. Report a few relevant delay measurements from your simulations. 
What happens if the load capacitance is increased to 1pf and 10pf?
 
Hints: This zip file contains examples of a library, the spice header that contains the BSIM3 Model and footer files for spice simulations.
 
Downloads:
 
Homework 3: (due date: Feb 8) 
Exercises  2.2, 2.4, 2.5, 2.6, 2.14, 2.15, 2.22
                 2.21, 2.3 (extra problem for EE 547 only)
 
 
Homework 4: (group project 1) (due date: Feb 22)
 
Download the following library. There are a few layouts missing in the library. You need to complete the physical  
layouts and perform spice analysis for every layout of different sizes (1X, 2X etc) in the same group that you have 
designed.  In other words, if you have designed AND4_4X, your analysis should be complete for all AND4 gates 
from sizes 1X to 4X. For loads we will use inverters of size (1X to 8X with increments of 1X).  More details will 
be discussed in the class. Please see me if you have questions.
 
 
Homework 5: (due date: Feb 29) 
Exercises  4.2, 4.3, 4.10, 4.11, 4.15, 4.24, 4.25  
                  4.12 (EE 547 only)
 
Homework 6: (due date: March 7) 
Exercises  4.30, 4.31 4.33, 4.34 
  4.35, 4.36 (for EE 547 only)
 
 
 
The Final Group Project.

IP-Library may be used in the projects. (Right-click and save).

 
 
Useful Links for Lecture1 (Fabrication of CHIPs)
 
Applied Materials
NEC Electronics

 

Reading Assignment: Please try to read  sections 1.7-1.12 as much as you can. You may not understand everything right now.

The Final project will be based on these sections. You may want to do some research on the web to find  relevant webpages that

deal with this topic.

 

 

      

Useful Links (For Spice and CAD tools)


BSIM3 model parameter
On subcircuits in Spice pdf file
Spice examples - sub-circuits etc
MOSIS models used in this course

Download Spice examples SPICE_Buffer.pdf
inv_cap.zip – Schematic design – an inverter with a capacitive load. Spice file is modified to allow various the inverter size. The parasitic capacitance is also estimated. 
inv_cap_optimization.zip – Optimization done on the previous inverter to make tpLH and tpHL equal to each other.

Download Spice examples SPICE_Buffer.pdf

MOSIS Design rules Use TSMC rules for 0.18 um 5 Metal 1 Poly SCMOS process.

Useful Links (Verilog)

Verilog notes-1 – part of this is taken from a Verilog training Manual from Cadence
Verilog notes-2

2 counters (one uses the behavioral code and the other uses “structural”)

Verilog manual

Verilog help from Carnegie Mellon University

Verilog help from UT Austin

Verilog help from ASIC world

Verilog or VHDL?