Final Project (March 10,
2008) (Total points 35)
In the Final Project you will design a multicycle MIPs
microprocessor described in section 1.7-1.12 of your textbook. The MIPS
(Microprocessor without Interlocked Pipelined Stages) m-processor was initially developed by
In the textbook we are given an 8-bit subset of the
well-known MIPS32 architecture. The 32
bit instruction code system is implemented using eight 8-bit general purpose
registers. Thus instruction can be loaded in chunks of one Byte at a time and
it takes 4 cycles to complete the process. The original MIPS computer has 111
instructions. However, this project will use only 8 instructions which
further simplify the ALU (Arithmetic Logic Unit) design in this course. These
are: LOAD, STORE, ADD, SUB, AND, OR, XOR, NOP.
For more details on the registers and the instructions that are
implemented, please read section 1.7 of your textbook.
In
the project you will need to create a behavioral and a gate-level Verilog code
and simulate the code for the main controller to verify that they are
functionally equivalent. You may wish to borrow and modify the behavioral code
from the appendix of the book. Please download from here.
Note that the Verilog code does not allow for all the instruction set shown in
Table 1.7. Please modify the Finite State Machine (FSM) and the code to add all
that are missing. You will eventually first put together the top-level
schematic and simulate using the SMARTSPICE program for the FSM. You should try
to verify that it executes MIPS instructions properly.
Much
of the design (layout, schematic and icon view) has been made available to you
in a library IP_Library_2008.jelib.
On my webpage you will find another electric library named IP_Library_final.jelib.
You may use any component from this library copy all that you need into
your team’s Library. In all cases be sure to check that a layout view is DRC
clean and that it matches the schematics. Always use the LVS (Layout vs.
Schematic) for the latter verification. LVS is called NCC in Electric. You may
need to repeat some the SPICE simulations with spice files extracted from the
layout assuming appropriate loads. In your layout, try not to use more than 3
metals. However, in dire circumstances, you may use metal-4 for a price.
Finally
you will use a 40-pin pad frame to connect your processor to the package using
gold bonding wires. The metal pads will be made preferably in metal-2 or
3. The sizes of the pads will be 100mm
´ 100mm.
The input pads should have circuitry to protect against ESD (Electro Static
Discharge) and the output circuitry should be able to drive an off-chip
capacitive load of at least 10 pf.
If you are not sure about the
specifications, please ask for clarifications. Please check this page often for revisions.
Target
dates:
March
28 |
Design
Review/Verilog code development and design verification complete |
April
4 |
Floor
plan complete, schematic check off and leaf cells complete |
April
18 |
Final
Project Check off |
April
22 |
Project
Presentation |
May
1 |
Final
Report Due by |
A
mini-report is due each Friday in March and April.