Development
and Evaluation of Slurry Compositions for Role of "planarization" in semiconductor device fabrication: The performance of a miniaturized semiconductor device is governed by its signal processing speed, which in turn is determined by the gate and interconnect delay times. The interconnect "RC delay" dominates the delay in signal processing, where R is the resistance of the wiring metal and C is the capacitance of the interlayer dielectric (ILD) used in the device. RC = [(rkl2)/(yd)], where r, l and d represent the resistivity, length and thickness of the wiring line, respectively; k and y denote the dielectric function and thickness of the ILD, respectively. Thus, decreasing the values of l and k are necessary to reduce the delay time. Integration of low-k ILD can also reduce cross talks and power dissipation in the device. Decreasing the value of l is generally accomplished through the technique of multilevel metallization (MLM). However, uneven topography is introduced as different levels are deposited in MLM, and such non-planar topography presents serious problem due to depth of focus limitations at short wavelength exposures in the lithography used for integrated circuit (IC) fabrication. Thus, surface planarization is necessary at each level of metallization in the MLM scheme, and chemical mechanical planarization (CMP, also referred to as chemical mechanical polishing) is the standard method currently practiced to accomplish this. As its name indicates, CMP combines chemical surface reactions with mechanical planarization. Mechanical performance of CMP is controlled by the polishing parameters, the pad and the abrasive(s) used. Chemical performance of CMP is governed by the reactions of slurry-additives with the sample surface, as well as by interactions of abrasive particles with the sample. Planarization of metal/alloy components used within the IC architecture represents a major part of the overall CMP process. Our CMP research focuses primarily on the fundamental aspects of metal/alloy CMP that dictate the material removal rates, planarization efficiency, uniformity across the wafer and defect-free quality of the polished surface. Complexities and requirements of CMP for advanced technology nodes Scaling of device structures has progressively introduced more challenges in the CMP technology used for IC fabrication. Pattern densities and wafer sizes have considerably increased in recent years, while feature sizes have shrunk in accordance with Moore's law and Dennard scaling. In the (constant field) Dennard scaling scheme, doubling of transistor numbers per unit chip area (occurring every 18-24 months) corresponds to a shrinkage of area by ½ for the same power. This translates to a scaling of lateral dimension by the square-root of ½, i.e., 0.7 (since [area] ~ [length]^2). The evolution of process-nodes from, 130 to 90, 65, 45, 32, 22, 14, 10 and 7 nm during 2004-2018 has basically followed this downscaling map by a reduction factor of 0.7 in each step. Owing to the limits of leakage current and processor frequency, the device structures in the post-Dennard (<65 nm) nodes have become more complex than those of earlier years. These intricacies are linked to the introductions of new materials, various <10 nm features, many additional CMP steps for FinFETs, middle of the line contacts, III-V systems, through-silicon vias, etc., in combination with the emergence of 300 (and 450) mm wafers. As a combined consequence of these developments, the criteria for achieving efficiency and precision in metal CMP have grown increasingly stringent and technically challenging. Pressure-minimized (low-P) polishing, previously identified as an essential requirement of metal CMP for the integration of mechanically fragile low-k ILDs, has been reinforced in most CMP schemes to avoid delamination of ultrathin nanoscale films used in the new technology nodes. Accordingly, metal CMP in its current state often relies on the chemical mode of material removal with diminished roles of mechanical abrasion. While this tactic of chemically promoted CMP requires strongly reactive chemicals in the CMP slurry, stricter requirements of defect control, on the other hand, constrains the choices of slurry additives to avoid dissolution, erosion and galvanic corrosion. Several challenges of slurry-ngineering for metal/alloy CMP originate from the difficulties of accommodating these widely varied demands. Electroanalytical and tribo-electroanalytical studies of metal/alloy CMP systems Laboratory scale experiments using model systems can offer a cost-effective yet efficient approach to addressing the aforesaid issues, especially during initial trials of formulating new slurry compositions. This approach is also useful to develop fundamental understanding of the planarization process. In these experiments we examine the detailed electrochemical response characteristics of strategically assembled model CMP (sample-slurry) systems by employing a variety of techniques, such as: potentiodynamic and galvanodynamic scans, chrono-amperometry, chrono-potentiometry, open circuit potential transients, and electrochemical impedance spectroscopy. In most cases, the experiments are performed in the presence of mechanical polishing of the sample with a CMP pad. A specifically designed tribo-electrochemical set up is used for these experiments. Small-scale test systems, composed of metal samples for CMP and judiciously chosen slurry additives, allow for a broad range of measurements with selective and collective variations of slurry chemistries, as well as electrochemical and mechanical control parameters. The material removal rates recorded in these experiments are characterized in terms of certain fundamental parameters of tribology (specific wear, tribo-corrosion rates) and electrochemistry (corrosion variables, rate constants) that are critical to develop fundamental understandings of complex CMP mechanisms. The analytical protocols of these studies have been described in a series of papers previously published from our laboratory. Electroanalytical and tribo-electroanalytical studies of post CMP Cleaning mechanisms Post CMP cleaning (PCMPC) is used to remove the chemical and particulate residues left on a wafer surface after CMP, and this is another crucial wet-processing step of IC fabrication. As in the case of CMP, the cleaning process also involves chemical and electrochemical (mixed-potential) surface reactions, coupled with tribology (action of "brushing" in this case). Fully understanding these system-specific mechanisms of PCMPC is necessary to guide the development of efficient cleaning solutions. Like CMP, the PCMPC step is also associated with rather intricate removal mechanisms that are rooted at the simultaneously operative functions of several additives used in the cleaning solutions. While the mechanical action of a brush is necessary in PCMPC, (electro)chemical reactions play central roles in preparing the CMP-processed surface for brush-cleaning. For instance, dissolution enablers remove impurity metal ions; chelating agents prevent re-deposition of these ions; pH adjusters weaken electrostatic adhesion of residual abrasives by changing their surface charges; selective oxide cleaners remove specific oxide sites, while leaving other oxide species for surface protection; other cleaning agents remove CMP residues of organic contaminants and corrosion inhibitor complexes. Sometimes corrosion inhibitors are also needed during PCMPC to avert re-oxidation and general/galvanic/photo-corrosion of the substrate. Controlled operation of these chemical actions of PCMPC requires careful selections and optimized combinations of the different cleaning agents. These tasks of preparing and screening PCMPC solutions can be addressed, once again in a cost-effective approach, by using lab-scale electroanalytical experiments. Adapting the methodologies developed in our electroanalytical and tribo-electroanalytical investigations of CMP systems, we have set up a systematic approach to evaluating PCMPC solutions for metals and alloys in a convenient, lab-based approach. Illustrative experimental results of these investigations have been reported. Electrochemical mechanical planarization (ECMP) ECMP combines electrochemically controlled material removal with low-P mechanical polishing where the main role of the latter step is to provide uniform planarization across the sample surface (that is, to facilitate selective material removal from protrusions over recess regions of the surface). Eectrochemical techniques are often used only as a "probe" of CMP mechanisms to analyze the corrosion/erosion features of CMP. In ECMP, electrochemical techniques can be used to both activate and understand the mechanism(s) of material removal. Our earlier works in the field of ECMP have focused on certain fundamental aspects of this method. The electrolytes used for these studies contained different combinations of nonspecifically adsorbing anions and complexing agents, with or without oxidizers. The activation voltages for material removal were designed as trains of repeated anodic voltage pulses. The voltage programs were planned to activate system-specific anodic reactions that lead to direct metal dissolution and/or electrochemical generation of surface films for mechanically assisted removal. The integrated charges of the resulting currents were used as a measure of electrochemically induced material removal.
|