EE365 Advanced Digital Circuit Design

Fall 2019

 

Course Information:

 

Catalog Description: An advanced course in digital circuit design. This course begins with an overview of electrical characteristics of logic gates, various standards for I/O buses and communication interfaces. Topics include hierarchical and modular design of digital logic circuits, simulation and synthesis of digital systems on programmable logic devices using computer-aided design software, and debug and verification of design using embedded and standalone logic analyzers.

 

Prerequisite: EE 264

 

Credits and Contact Hours: 3 credits, 3 contact hours per week

 

Textbook (recommended, not required)

 

Digital Fundamentals, A Systems Approach, Thomas L. Floyd, Publisher: Prentice Hall:

ISBN-10: 0132933950 ISBN-13: 9780132933957 Publisher: Prentice Hall 2013

 

Demo Board

Cora Z7: Zynq-7000 Single Core and Dual Core Options for ARM/FPGA SoC Development

https://store.digilentinc.com/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/

 

Required/Elective/Selected Elective:

 

Required for Computer Engineering

Elective for Electrical Engineering and Software Engineering

 

Goals for the Course:

Course Objectives and Demonstrable Learning Outcomes:

 

1.      Learn the electrical characteristics of logic gates and I/O standards and understand how these devices function in a typical application circuit, including interfacing with other circuit elements. ABET Criterion 3 Outcomes (1)

2.      Students should learn how to design and test practical digital systems using standard medium scale and large scale integrated circuits, including programmable logic circuits. ABET Criterion 3 Outcomes (1, 2 and 6)

3.      Learn how to use HDL design entry methods and constraints in FPGA tools, create testbench for behavioral simulation, perform logic synthesis, debug and test design outputs using logic analyzers. ABET Criterion 3 Outcomes (1, 2, and 6)

4.      Students should gain experience with a variety of standard digital memory circuits and subsystems, and should understand their internal design and their application in more complex systems. ABET Criterion 3 Outcomes (1 and 2)

5.      Students should be able to communicate technical information in writing using documentation standards for digital designers. ABET Criterion 3 Outcomes (3)

6.      Students should engage activities that promote life-long learning. ABET Criterion 3 Outcomes (7)

 

Criterion 3 Outcomes Assessed by the Course:

 

Outcome 6. An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions (Assess course learning objectives 2 and 3).

Outcome 7. An ability to acquire and apply new knowledge as needed, using appropriate learning strategies (Assess course learning objective 6)

 

Assessment Methods

 

1.      Homework and Projects will be given that require students to demonstrate the ability to complete specific designs. Two home project based exam will be given that test knowledge necessary for analysis and design of digital circuits. [Measures Criterion 3 outcome 6]

2.      Successfully design, implement and test digital systems by carrying out independent research, using the web, library references and other resources. [Measures Criterion 3 Outcome 7]

 

Topics Covered:

         Introduction: overview of digital concepts and electrical characteristics of logic gates, various standards for I/O buses and communication interfaces, practical logic design, data books and documentation

         Popular serial buses: SCI, SPI, I2C and JTAG

         Timing in combinational circuits, Loading, Noise Margins, Logic gate Fan-out, Timing hazard

         Synchronous design using state machines and timing considerations

         Designs using VHDL and CAD tools, programmable logic: FPGAs (Altera and Xilinx)

         Logic Simulation and use of Logic analyzers

         Design using embeddable development platforms: VHDL and C

         Testability

 

Course Policies and Grading:

 

Approximately 4-5 homework problem sets will be assigned. Design projects will be given approximately once every 2 weeks. Students are required to work on projects in a group of two; groups may not share information with one another. Design projects will be demonstrated in the lab. Most of the design projects will require submitting well-organized technical reports. Students will be writing individual and/or group reports. There will be two exams and a comprehensive final exam (or a project) as shown below.

 

Take home project I 

15%

October 19-22

Take home project II

15%

November 16-19

Homework

10%

 

Projects+ Technical Reports

50%

 

Final Exam/Project

10%

 

 

Instructor:

Abul Khondker

CAMP 134, phone: x-2127

Office hours: WF 9:30-10:30 am, TTh 10:30 am-12:30 pm (Tentative)

Webpage: http://people.clarkson.edu/~akhondke/

Email: khondker@clarkson.edu