Advanced Digital Circuit Design
I. Course Description
An advanced course in digital circuit
design, this course begins with a review of switching algebra and combinational
design, programmable logic devices, and combinational circuits including
encoders/decoders and multiplexers/demultiplexers. Sequential circuits using
latches, flip-flops, ROM and RAM and also reviewed. Topics in sequential
circuit design are treated, including finite state machines, Mealy and
II. Prerequisites EE 264
III. Textbook and Design Board
Digital Fundamentals with VHDL by Thomas F Floyd, Prentice Hall, 2003. (This is the same textbook that was used in EE264)
Altera DE1 Board (Required – costs $149+tax+S/H). University Bookstore will sell this at a lower price.
IV. References source for data on xilinx CPLDs, FPGAs
V. Course Topic Outline (Textbook references are given in brackets)
Introduction. Overview of digital concepts
Review of basic Number systems
Review of Boolean Algebra and combinational logic design
Timing in combinational circuits, Loading, Noise Margins, Logic gate Fanout, Timing hazard
Programmable logic: PLDs, FPGAs, etc.
Practical logic design: data books, CAD tools, documentation
MSI and VHDL implementations of building block components:
decoders, muxes, tri-state logic, adders, etc.
Design examples using combinational components
Review of sequential logic elements and systems: flip-flops, counters and shift-registers
Clocked synchronous state machines
Synchronous design using state machines
Practical timing considerations and designs using VHDL
Memory components (ROM, SRAM, DRAM)
VI. Course Objectives
VII. Learning Outcomes
VIII. Assessment Methods
IX. Course Policies and Grading
Problem sets will be given approximately every week. In some cases, you will be encouraged to work on these in small groups. Some solutions are available at the textbook web site; others may be covered in class. Ability to do these problems is important for satisfactory performance on the exams. Design problems will be given approximately once every 3 weeks. You may work alone, or in a group of two only. Groups may not share results with one another. Design problems will be collected and graded. There will be two exams and a comprehensive final exam as listed in the schedule below.
Exams (in class) 30 % (October 16
November 29, 2007) (Open Book)
home Exam 20
October 25 November 1
Homework 15 %
Projects 35 %
Dr. Abul Khondker
CAMP 134, phone: x-2127
Office hours: MWF 10:00-11:30 noon, TTh 11:00-12:00 noon
Homework 1 (Due date: September 11, 2007)
Express the charge of an electron 1.602176487 × 10-19 (ref: http://en.wikipedia.org/wiki/Elementary_charge)
in IEEE single and Double precision floating point (normalized) number system.
Problems from Chapter 3: 24, 25, 26, 49 (block diagram is enough)
Problems from Chapter 14: 1, 2, 4, 6, 9, 11, 16, 20, 22, 23 (submit only the even numbered problems)
Solution HW#1: Charge of an electron in single precision.
Homework 2 (Due date September 25, 2007)
Problems from Chapter 14: 25, 26, 27, 28
Problems from Chapter (a) & (d), 40 (d), 46 (b) & (c), 50 (b)
Investigate if problems 38(a) and 50(b) can have glitches. If so identify
the situation, i.e. if it a static-1 or static-0 hazard. Fix the circuit to prevent the glitches if any.
Solution HW#2: Click here
Homework 3 (Due date October 4, 2007)
Problems from Chapter 6: 14, 15, 16, 17
Problems from Chapter 9: 24, 25, 26, 27
Solution HW#3: Click here
Homework 4 (Due date November 15, 2007)
Solution HW#4 Click here
Solution to Hour Exam
All project should be done by a group of two students. If you do not have a partner, please send me an email. Please submit a group project report.
Project 0. (10 points) Click here to visit Altera’s website for tutorials and Lab exercise. You are a asked to complete the Tutorial “Introduction to the Quartus II Software” VHDL version. This is a warm-up for future projects. We will meet on Tuesdays or Wednesdays after 4:00 pm in the ECE lab. However, before that you will need to install the software on your computer or use the PCs in the lab. If you need help in the lab, please call me at x2127. If you are done before the lab period, I will try to check your design.
Project 1. (10 points) Click here to visit Altera’s website for tutorials and Lab exercise. You are a asked to complete the Tutorial “Using the Library of Parameterized Modules (LPM) and Timing Considerations” VHDL version. Due date: October 9 and 10 in lab. You may work in a group of 2.
Project 2. (20 points) Design a 8 bit binary up-counter using Altera’s DE1 board.. The counter should run with an “effective” clock that has a frequency of 1 Hz. You must not use clock dividers; instead use clock enables to accomplish the task of counting at 1 Hz. The counter will have a clear button (KEY0) to initialize the sequence to 0X00 when it is 1, and a count switch (SW0) which when it equals 1 enables the counting sequence. The output should be displayed on the LEDs on the DE1 board as well as on the 7 segment displays. The least significant bit (LSB) of the counter should be displayed on LEDR0 and the MSB on LEDR7. The 7-seqment displays should use 2 HEX numbers to represent the 8 bit numbers.
The project should be done by a group of two students. Please submit a group project formal report.
All project reports from now should contain:
ü An executive summary
ü Problem description
ü Design Problem Statement (Interpretation of the Specification)
ü Problem Decomposition (use functional blocks)
ü Significant details of design process
ü Alternative designs (if applicable)
ü Design documentations: Schematics documenting your hardware design, VHDL,
and test bench files (if any), Software design, i.e. flowchart or pseudo code
ü Performance Results and Analysis
ü References (if any)
Include the VHDL and in the report and a summary of what resources were used on the Cyclone II FPGA. The project should be demonstrated in the lab on October 23 and 24.
Project 3. (30 points) Design a 8-bit binary up-down counter for a 1 Hz effective clock. The counter should count down when button KEY0 is pressed and should count up when it is released. It should have a clear button (KEY1) that initializes the sequence (asynchronously) to 0X00 when it is pressed. Also it has a count button (KEY2) which disables the counting sequence when it is pressed. When button KEY3 is pressed, it stops counting & loads (synchronously) a 8-bit number (N) into the counter. The 8-bit number to be loaded is provided using the 8 switches (SW7-SW0) on the DE1 board. The counting process will repeat itself between 0 and N in the up sequence and between N and 0 in the down counting sequence. The output should be displayed on the LEDs on the DE1 board as well as on the 7 segment displays. The least significant bit (LSB) of the counter should be displayed on LEDR0 and the MSB on LEDR7. The 7-seqment displays should use 2 HEX numbers to represent the 8 bit numbers.
The project should be done by a group of two students. Please submit a group project formal report. Follow the directions given on Project 2. Include the VHDL and in the report and a summary of what resources were used on the Cyclone II FPGA. The project should be demonstrated in the lab on October 30 and 31.
Project 4 (50 points Total. 20 points for implementing the keypad only – details later) Due date: December 5 2007.
Design a SRAM based "programmable 8-bit counter of arbitrary sequence" that runs on an one Hz generated clock. It should have a clear (or reset) button (KEY0) that initializes the sequence (asynchronously) to 0X00 and erases the sequence when it is pressed. The programming will be accomplished using a keypad attached to the DE1 board via the digital breadboard (DBB1) and the 40 pin IDE ribbon cable. These keypad keys are 0-9, A-F and three other keys called H, L and ‘shift’. Download the 19KeyPad header pin diagram.
Note that the DE1 board has a 512 Kbyte of fast asynchronous SRAM, surface mounted on the board. The SRAM address for each is 18-bit long (needed for 256K memory locations of 16-bit wide). We will use only 8-bits in this project. Theoretically, the arbitrary counter sequence (of 8-bit) can be 2x256K long. However, since we do not have time to "program" the counter to by hand, we will restrict to a length less than 256. In other words, the project will use memory addresses from "00 0000 0000 0000 0000" to "00 0000 0000 1111 1111". For simplicity we will refer to the address as from OX00 to OXFF with the understanding that the rest of the higher order address bits are always 0s.
Note: we will refer to the four 7-segment LED displays on the DE1 board by the names of the anodes, i.e., by HEX3, HEX2, HEX1 and HEX0.
You must design your SRAM controller. Here is a link that you may find useful for your design. You cannot use Altera’s IPs. The project report is due on Dec. 7. The implemented project should be demonstrated in lab by December 5, 2007.
A sample simulation of a SRAM controller.
Learn VHDL by example – A Tutorial
Logic Gates etc.
Logic Families – a short summary