EE441/EE541 Electronic Devices for IC Simulation
Course Outline, Spring 2009
Class web
site: http://www.clarkson.edu/~mcheng/EE441-541/EE441_541.html
Catalog Data: EE441 Electronic Devices for IC Simulation,
3 credits
Prerequisites:
ES260 & EE341
Study of modern electronic devices, including p-n junctions, bipolar
junction transistors (BJTs) and
metal-oxide-semiconductor field-effect transistors (MOSFETs),
for integrated circuit applications. SPICE device models are introduced, and
several SPICE simulation projects are given for integrated circuit
analysis. This course provides a
foundation for understanding SPICE device models and the basics of the
microelectronic technology.
Instructor: Ming-Cheng Cheng
Office: 138 CAMP, Phone: 268-7735; Email: mcheng@clarkson.edu
Tentative
Office Hours: 2:15-3:30pm, Tuesday
2:30-4:00pm, Wednesday
Class Schedule and Location: 4:00pm-5:15pm,
Tuesday & Thursday, CB268
Textbook: H. Craig Casey, Jr, Devices for Integrated Circuits, John Wiley & Son, 1999.
References: Sheng S. Li,
Semiconductor Physical Electronics,
G. W. Neudeck, The PN Junction Diode, Addison-Wesley
G. W. Neudeck, The Bipolar Junction Transistor, Addison-Wesley
R. F. Pierret,
Field Effect Devices, Addison-Wesley, 1984.
S. M. Sze, Physics of
Semiconductor Devices, 2nd edition, John Wiley & Sons
SPICE Tool: Any SPICE tool can be used for the projects, such as LTSpice (http://cmosedu.com/cmos1/ltspice/ltspice.htm, AIM-Spice (www.aimspice.com) or PSpice (https://www.cadence.com/products/orcad/pages/downloads.aspx).
Course Contents:
Chapter 2 Electrons in Solids
Chapter 3 Carrier Transport & Recombination
Carrier concentration, mobility, drift and diffusion processes, recombination, and basic semiconductor equations
Chapter 4 p-n Junctions: I-V Behavior
Energy band diagram, depletion approximation, pn junction electrostatics, pn junction characteristics,
Chapter 5 p-n
Junctions: Reverse Breakdown & Junction Capacitance (a short Spice project will be assigned)
Junction breakdown, depletion and
diffusion capacitances, and SPICE diode model.
Chapter
7 MOS Capacitors
Flat band voltage, MOS capacitance, accumulation
and inversion, and threshold condition and voltage
Chapter
8 MOS Field Effect Transistors (a short
Spice project will be assigned)
IV characteristics, small signal model, basic MOSFET SPICE model
Chapter 9 Bipolar Transistors (a short Spice Project will be assigned)
BJT operation, minority carrier injection, current gain and IV characteristics, Ebers-Moll model, small signal model, basic BJT SPICE model
There will be
approximately 5-6 homework assignments and 3 Spice Projects for this class.
Extra problems for graduate students will be included in some homework
assignments. The final project for graduate
students requires a formal project report and present.
Tentative Date for the First Midterm Exam: Tuesday, October 6, 2009
Tentative Date for the Second Midterm Exam: Thursday, November 19, 2007
Grade Policy:
|
Graduate Students (EE541) |
Undergraduate students (EE441) |
||
|
HW Assignments |
10% |
HW Assignments |
15% |
|
Two Midterm Exams |
2´20% |
Two Midterm Exams |
2´22.5% |
|
3 Spice Projects |
24% |
3 Spice Projects |
40% |
|
Final Project & Presentation |
26% |
|
|
|
Total |
100% |
Total |
100% |
* If the student does not turn in any HW assignment or any project, he
or she will receive an F grade.
Exam Policy:
Closed
book; only one sheet of
notes for equations is allowed.
Course Learning Outcomes: