Project 2. (5 points)

(a) Using the Xilinx's Foundation software in the HDL design flow , describe the 8-input 74x148 MSI encoder chip in VHDL. Use the device named 95108PC84 (a PLD device of Xilinx's XC9500 family) in this project. The logic diagram of the chip is shown in Figure 5-50 on page 379. The VHDL code must be written using the "dataflow" design elements. Verify using the Xilinx software that the VHDL entity-architecture is correct. This means the 8-3 Encoder is functioning as described in Table 5-23.

(b) Use the 74x148 VHDL code from part (a) to describe a 32 input 5 output encoder that is described on page 380 (Fig 5-51). The VHDL code must use the "structural" design elements in which the VHDL code from part (a) will be instantiated as component 4 times.

For hints, please study the "4-16 decoder using two-74x138 ICs" (VHDL examples #4 and #2) shown on my main EE365 page. In example #2 two halves of the 74x139 (2-4) decoder were used to build a 3-8 decoder.

You may work in teams of two, with no collaboration between teams. The project report should include the VHDL code as well as the simulation waveform printouts from the software. You should turn in a printed schematic of each design, two or three sample simulations. Be sure to include enough information on the plots such that it is clear that the designs are working as expected. Remember that by simply the reporting the VHDL codes/schematic or plots are not enough. You must include in the report the relevant circuits indicating clearly the SIGNAL names that you have used in the architectures for any entity and describe the plots with sufficient details.

Due date: Nov 1, in class. Good luck.