Project 1. (5 points)

Using the Xilinx's Foundation software, design a 4-to-16 decoder using two 74x138 MSI chips.

(a) Use the dataflow VHDL program for the 74x138 and Xilinx's Schematic flow editors and simulators. Also, be sure to use the 9500 series CPLD for your design.

(b) Using the "demolib" library from my webpage, redesign the 4-to-16 decoder with two 74LS138 chips in the schematic flow. This time using the Timing simulation determine the typical delays between the inputs and the output.

You may work in teams of two, with no collaboration between teams. You should turn in a printed schematic of each design, two or three sample simulations. Be sure to include enough information on the plots such that it is clear that the designs are working as expected. Remember that by simply the reporting the VHDL codes/schematic or plots are not enough. You must include in the report the relevant circuits indicating clearly the SIGNAL names that you have used in the architectures for any entity and describe the plots with sufficient details.

Due date: October 23, in class. Good luck.