EE 560 Hardware/Software System Design and Verification
Fall 2009

I. Course Description

Fundamental concepts of digital system design and verification with emphasis on modeling methodology, specification languages, and system verification. Languages and tools for system specification, modeling and verification will be discussed, including SystemC, Verilog and VHDL.

II. Prerequisites

Knowledge of C/C++ and Verilog or VHDL.

III. Textbook(s)

SystemC from The Ground Up by David C. Black and Jack Donovan, Springer, ISBN 0-387-292240-3(SC), 1-4020-7988-5(HC), 2006 (required)

A systemC Primer by J. Bhasker, Star Galaxy Publishing, ISBN 0-9650391-2-9, (second ed.) 2004 (highly recommended).

IV. Course Topic Outline

1. Overview of System Design, Transaction Level Modeling (TLM)-based Methodology

2. Introduction to SystemC

3. SystemC Data Types

4. Modules

5. Time, Concurrency, Events & Processes

6. Structure, Module Hierarchy, Ports, Channels, signals and Interfaces

7. Modeling, Functional, TLM and RTL modeling

8. Verification using SystemC

9. Other Advanced Topic

V. Software and Standards

SystemC standards (download from http://www.systemc.org/downloads/standards/)

· SystemC, Release 2.2.0

· Verification Library (SCV), Release 1.0p2

· TLM release 2.0.1

Platform(s)

· Ubuntu

· Windows XP or Vista

C/C++ compilers

· gcc/g++ version 4.2.4 or less

· Eclipse

· Microsoft Visual Studio (or Express) 2008

VI. Assessment Methods

Homework/Projects will be given that require students to demonstrate the ability to do specific designs.
Two exams (could be both take home exams) and a Final Exam will be given that test knowledge necessary for analysis and design of digital circuits.

VII. Course Policies and Grading