EE365: The Final Project (20 points)
Updated: Saturday, Nov 17, 2001 at 4:25 pm
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The Traffic light controller
Design a traffic light controller that employs a digital system which switches lights
on or off in a sequence that enables the traffic to flow and pedestrians to cross the
road soon after they press a Walk button. We consider a simplified intersection at a
EW (East-west) Highway and a NS (North-South) county road. There are walk buttons that
a pedestrian can press at anytime.
Here are the main features of the controller:
The EW Highway is heavily travelled. It remains green most of the time unless
(a) a vehicle nears the signal light in the NS direction or (b) a pedestrian presses
the walk-button. However, when one of these events take place, the EW-light remains green for about 6-7 cycles before changing to red. Assume that an electronic sensor detects the presence of a vehicle on the NS bound street as it nears the intersection.
The NS street gets about 4 clock cycles of green.
For simplicity, assume there is no yellow light.
If a pedestrian presses the button the NS or EW signals will change to red (after they remain green for the required times), and the pedestrian will then get about 3 clock cycles to cross the street or the highway.
Once a request from a pedestrian is registered no further request will be accepted
from the pedestrians even of anyone else presses the button until after traffic flows
in one or the other direction.
Although a Pedestrian has a higher proirity over vehicles, make sure that the traffic flow is not stopped in any direction by a fun-loving pedestrian.
The design You may (should?) work in a group of two. You must not discuss the contents of your work with other groups. Since this is a design project, I can imagine many unique approaches to solve the problem. So if two projects look similar in ideas and/or content and/or style, I have to assume that these two groups have had some interactions.
Use XC9500 series CPLD in this project, If you use MUXs, D-flip flops etc, use VHDL code based macros as part of your circuit.
Simulate your result using the "timing mode" rather than the "functional mode" of the Xilinx tool.
The report must be written in a professional manner. Which means it must be thorough yet concise so it does not take a long time to read the report. Your projects must accompany a floppy disk with "archived versions" of the Xilinx project.
The diskette will (may) not be returned.
The grade on the project will depend on the following:
your method of approaching the design problem (This will test your creativity)
thoroughness of your work that makes these projects as "near-flawless"
as can be accomplished (This will be the test of your knowledge),
and demonstrating "clearly" with simulations that your design works for a number of test
conditions (that means as you make progress in your work, keep in mind you have to test it too). This is called "design for testability".
Due date Thursday, December 6 by 4:00 pm. The project will be accepted until Dec 10. Howvever the maximum grade awarded will be reduced to 15.