EE 365

Advanced Digital Circuit Design

Fall 2001

I. Course Description

An advanced course in digital circuit design, this course begins with a review of switching algebra and combinational design, programmable logic devices, and combinational circuits including encoders/decoders and multiplexers/demultiplexers. Sequential circuits using latches, flip-flops, ROM and RAM and also reviewed. Topics in sequential circuit design are treated, including finite state machines, Mealy and Moore models, state diagrams and state tables, optimization, asynchronous sequential circuits, and races and hazards. In addition, implementation of sequential circuits with programmable logic devices is discussed, as are topics in logic circuit testing and testable design.

 

II. Prerequisites

EE 264

 

III. Textbook

Digital Design Principles and Practices, 3rd ed. by Wakerly. Prentice Hall, 2000.  (required)

 

IV. References

Digital circuit data book (available online):

            www.ti.com (search by part name e.g. 74LS04 or use the functional index)

            www.latticesemi.com  source for data on GALs

            www.xilinx.com/partinfo/databook.htm  source for data on xilinx CPLDs, FPGAs

Textbook web site www.ddpp.com  (includes an appendix on basic electric circuits that is useful if you don’t remember, or didn’t take ES 250)

 

V. Course Topic Outline             (Textbook references are given in brackets)

1.      Introduction.  Overview of microelectronic devices and digital signals. [Chaps. 1 and 3]

2.      Review of basic Boolean Algebra and combinational logic design.  [Chap. 4.1-4.3]

3.      Practical logic design: data books, CAD tools, documentation [Chap. 4.7, 5.1, 11.1]

4.      Timing in combinational circuits [Chap. 4.5, Chap. 5.2]

5.      Programmable logic: PLDs, FPGAs, etc. [Chap. 5.3 and 8.3]

6.      MSI and VHDL implementations of building block components:
      decoders, muxes, tri-state logic, adders, etc. [Chap. 5.4-5.11]

7.      Design examples using combinational components [Chap. 6.1 and 6.3]

8.      Review of sequential logic components: S-R latch, D latch, D flip-flop. [Chap. 7.1-7.2]

9.      Clocked synchronous state machines [Chap. 7.3- 7.5]

10.    Synchronous design using state machines [Chap. 8]

11.    Practical timing considerations and designs using VHDL  [Chap. 9.1-9.2]

12.    Memory components (ROM, SRAM, DRAM) [Chap. 10]

13.    Testability [Chap. 11.2]

VI. Course Objectives

1.  Students should learn the electrical characteristics of CMOS and TTL logic gates and should understand how these devices function in a typical application circuit, including interfacing with other circuit elements.

2.      Students should learn how to design practical digital systems using standard medium scale and large scale integrated circuits, including programmable logic circuits.

3.      Students should learn how to use modern CAD tools including schematic capture editors, simulations, and logic synthesis compilers based on VHDL.

4.      Students should gain experience with a variety of standard digital memory circuits and subsystems, and should understand their internal design and their application in more complex systems.

 

VII.  Learning Outcomes

1.      For CMOS and TTL logic families, students will be able to explain the meaning of electrical characteristics such as noise margin, input and output voltages and currents, and timing characteristics.  Students will be able to design interfaces between devices from these logic families and other electronic devices. [Objective 1]

2.      Students will be able to design practical digital systems using standard MSI parts and programmable logic. [Objective 2]

3.      Students will be able to use CAD tools to produce a schematic of a digital design and to simulate the design. [Objective 3]

4.      Students will be able to express a digital design in VHDL and use a VHDL compiler to synthesize the design in programmable logic. [Objective 3]

5.      Students will be able to use standard digital memory devices as components in complex subsystems. [Objective 4]

 

VIII.  Assessment Methods

1.      Homeworks (some design problems) will be given that require students to demonstrate the ability to  do specific designs. [Measures outcomes 1-5]

2.      Two exams and a final exam will be given that test knowledge necessary for analysis and design of digital circuits. [Measures outcomes 1, 2, 4, 5]

 

IX.  Course Policies and Grading

Problem sets will be given approximately every week.  In some cases, you will be encouraged to work on these in small groups.  Some solutions are available at the textbook web site; others may be covered in class.  Ability to do these problems is important for satisfactory performance on the exams.  Design problems will be given approximately once every 3 weeks.  You may work alone, or in a group of two only.  Groups may not share results with one another.  Design problems will be collected and graded.  There will be two exams and a comprehensive final exam as listed in the schedule below.

 

            Grading:

                        Homework                  30 %

                        Exams                         30 %     October 11,  and  November 15

                        In Class quiz average            15 %

                        Final Exam               25 %   

X.  Instructor

            Dr. Abul Khondker

            CAMP 134,  phone: x-2127

            khondker@clarkson.edu

            Office hours:  MWF 10-12 noon